The present invention relates to a semiconductor device and a process for producing a semiconductor device. More specifically, the present invention relates to a semiconductor device having a novel structure and comprising a bulk-defect region and a denuded region, these regions being formed by means of an intrinsic gettering, an ion implantation, or a diffusion technique, and to a process for producing the semiconductor device.
In the art, by means of the intrinsic gettering technique, a bulk-defect region is selectively formed in a single crystalline silicon wafer produced by means of a pulling method (hereinafter referred to as a CZ wafer). The CZ wafer contains oxygen. A bulk-defect region is selectively formed by precipitating the oxygen as crystal defects in the CZ wafer. More specifically, in the intrinsic gettering technique, the CZ wafer is heat treated at a temperature of 1000.degree. C. or higher so as to remove the oxygen contained in the surface portion of the CZ wafer due to outward diffusion of the oxygen. As a result, the surface portion of the CZ wafer has a low oxygen concentration and later becomes a denuded region. Subsequently, the CZ wafer is subjected to a heat treatment at a temperature of approximately 650.degree. C. so as to form nuclei in the crystal in the inner part of the CZ wafer. The CZ wafer is next subjected to heat treatment at a temperature of approximately 1050.degree. C. so as to transform the nuclei in the crystal into crystal defects. The nuclei in the crystal in the inner part of the CZ wafer are transformed into crystal defects due to the presence of oxygen in the CZ wafer. The oxygen, which is incorporated into the CZ wafer during the manufacture of the wafer, allows nuclei to form in the crystal and to later be transformed into crystal defects. Alledgedly, carbon, which is contained in the CZ wafer, precipitates during the transformation of the nuclei into crystal defects.
An example of a known semiconductor device which is produced by utilizing the intrinsic gettering technique is hereinafter described with reference to FIG. 1.
In the CMOS semiconductor device shown in FIG. 1, the CZ wafer 1 comprises a denuded region 2 at the surface portion thereof and bulk-defect region 3 at the inner portion thereof. In the CMOS, N-channel transistor 4 and P-channel transistor 5 are formed in denuded region 2, and P well 15, N.sup.+ -type source region 6, N.sup.+ -type drain region 7, gate electrode 8, and a gate insulating film (not shown) are the elements of the N-channel transistor 4. Similarly, P.sup.+ -type source region 9, P.sup.+ -type drain region 10, gate electrode 11, and a gate insulating film (not shown) are the elements of P-channel transistor 5. One of the reasons for forming the N-channel transistor 4 and the P-channel transistor 5 of the CMOS in the denuded region 2 is that contaminant substances, which may be incorporated into denuded region 2 through the surface thereof during the production of a CMOS, can be captured by the bulk-defect region 3, with the result that the properties of the N-channel transistor 4 and the P-channel transistor 5, especially the junction property, are stabilized. Another reason for forming transistors 4 and 5 is that electron-hole pairs which are generated due to .alpha.-rays are captured in bulk-defect region 3.
The present inventors studied the electrical properties of conventional CMOSs and discovered that since the distance (dp) between the bulk-defect region 3 and either the P.sup.+ -type source region 9 or the P.sup.+ -type drain region 10 of the CMOS is greater than the distance (dn) between the bulk-defect region 3 and the P well 15 of the CMOS, various problems result. One of the problems is that when .alpha.-rays are emitted into the CZ wafer 1, pairs of electrons (black dots) and holes (white dots), i.e., electron-hole pairs, are generated and several holes then diffuse toward the P well 15. Since the diffusion length of the electron-hole pairs is long in the denuded region 2 due to the absence of crystal defects, it is highly possible that diffusion of the holes toward the P well 15 mentioned above can generate a leakage current in the PN junction 12, which is formed between the P well 15 and the denuded region 2 which has an N-type conductivity. A leakage current can cause noise.
Hereinafter the, N-channel transistor 4 and the P-channel transistor 5 are collectively referred to as MOS transistors 4 and 5.
Another problem is that when the inversion layers 13 are formed during energization of the MOS transistors 4 and 5, electron-hole pairs are generated, due to impact ionization, in the depletion layer 14 around the N.sup.+ -type drain region 7 or the P.sup.+ -type drain region 10. The electrons and/or holes then move toward the surface of the CZ wafer 1. During this movement, no recombination of the holes and electrons occurs in the bulk-defect region 3 due to the fact that dp&gt;dn. Instead, a flow of holes into the P well 15 occurs, causing the potential of the P well 15 to increase, and, as a result, a leakage current can be generated in the PN junction 12. The generation of a leakage current becomes serious when the MOS transistors 4 and 5 are miniaturized, and a so-called latch up frequently occurs during energization of the CMOS. Reference numeral 14 indicates schematically the depletion layers which are formed around the sources and drains of the MOS transistors 4 and 5 due to the PN junctions, which are not numbered.
The present inventors generally noted the following points concerning a conventional semiconductor device: 1) In a conventional semiconductor device, at least two semiconductor elements have a nonuniform depth when measured from the surface of the semiconductor substrate and the denuded region and the bulk-defect region of the semiconductor device have a uniform depth when measured from the surface of the semiconductor substrate; 2) For this reason, a leakage current can be generated in the PN junction of a semiconductor device; 3) Due to the possible generation of a leakage current, the information holding time is shortened and refresh failure results for a dynamic memory semiconductor device and; 4) Due to the leakage current, isolation of the semiconductor elements becomes incomplete for a bipolar semiconductor integrated circuit device when the device is highly integrated.